1. Field of the Invention
The present invention relates to a field programmable gate array (FPGA) architecture.
More particularly, the present invention relates to structures for coupling routing resources to one another in an FPGA architecture.
2. Background Art
In the FPGA art, both antifuse based programmable architectures and SRAM based reprogrammable architectures are well known. In an FPGA, the logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements. In a antifuse based device, the number of the programmable elements far exceeds the number of elements in an SRAM based device because the area required for an antifuse is much smaller than an SRAM bit. Despite this space disadvantage of an SRAM based device, SRAM based devices are implemented because they are reprogrammable, whereas an antifuse device is presently one-time programmable.
Due to the area required for an SRAM bit, a reprogrammable SRAM bit cannot be provided to connect routing resources to each other and the logic elements at every desired location. The selection of only a limited number of locations for connecting the routing resources with one another and the logic elements is termed “depopulation”. Because the capability to place and route a wide variety of circuits in an FPGA depends upon the availability of routing and logic resources, the selection of the locations at which the programmable elements should be made with great care.
Some of the difficulties faced in the place and route caused by depopulation may be alleviated by creating symmetries in the FPGA. For example, look-up tables (LUT) are often employed at the logic level in an SRAM based FPGA, because a LUT has perfect symmetry among its inputs. The need for greater symmetry in a reprogrammable FPGA architecture does not end with the use of look-up tables. It also extends to the manner in which routing resources are connected together, the manner in which routing resources are connected to the logic elements, and further symmetrization internal to the logic block. Without a high degree of symmetry in the architecture, the SRAM memory bit depopulation makes the place and route of nets in an SRAM based PPGA difficult.
It is therefore an object of the present invention to improve the symmetry in the logic block of the FPGA architecture to improve the routability of nets within the logic block and nets that are driven from inside the logic block that drive inputs both inside and outside the logic block.